In fabrication and application of integrated circuit (IC) chips, along with continuous improvement in very large scale integration technologies, current CMOS IC fabrication technology has entered a deep sub-micron stage. Dimensions of MOS devices continue to shrink, thicknesses of gate oxide layers become thinner and thinner, and voltage resistance capability of the MOS devices have significantly decreased. Thus, damage to the ICs due to electrostatic discharge (ESD) has become increasingly significant. Therefore, ESD protection for ICs has become particularly important.
To increase the capability of ESD protection, an ESD protection circuit is often connected to an input/output (I/O) interface terminal (e.g., an I/O pad). The ESD protection circuit is an internal circuit in a chip for providing an electrostatic current discharge path in order to avoid electrostatic breakdown of an internal circuit.
Parts that are commonly used in a conventional ESD protection circuit include an NMOS transistor with a grounded gate, a PMOS transistor with a gate connected to a power supply, a silicon controlled rectifier (SCR), and the like. The NMOS transistor with a grounded gate has good compatibility with CMOS industry. Therefore, the NMOS transistor with a grounded gate has been widely used.
FIG. 1 illustrates a schematic structural diagram of a conventional ESD protection circuit. A drain of an NMOS transistor 13 is connected to an input/output (I/O) interface terminal 15. A gate and a source of the NMOS transistor 13 are connected to a ground terminal 16. When a large electrostatic voltage or electrostatic current is generated in the I/O interface terminal 15, static electricity is discharged to the ground terminal 16 via a parasitic NPN transistor in the NMOS transistor 13.
Details are illustrated in FIG. 2, which illustrates a cross-sectional schematic structural diagram of the NMOS transistor in FIG. 1, which includes a semiconductor substrate 100. A P-well 101 is provided in the semiconductor substrate 100. A gate 103 of the NMOS transistor is provided on the semiconductor substrate 100. A drain region 102 and a source region 104 of the NMOS transistor are respectively provided in the P-well 101 on two sides of the gate 103. The drain region 102 of the NMOS transistor is connected to the I/O interface terminal 15. The source region 104 and the gate 103 of the NMOS transistor are connected to the ground terminal 16.
A P-type doped region or a P-region 105 is further provided in the P-well 101 on a source region 104 side. The P-region 105 is connected to the ground terminal 16. A shallow trench isolation structure 106 is provided between the P-region 105 and the source region 104. The drain region 102 of the NMOS transistor configures a collector region of a parasitic NPN transistor 17. The source region 104 of the NMOS transistor configures an emitter region of the parasitic NPN transistor 17. The P-well 101 at bottom of the gate 103 configures a base region of the parasitic NPN transistor 17.
When electrostatic charge accumulates on the I/O interface terminal 15, current flows from the drain region 102 via a well region resistance 18 to the P-region 105 and thereby generates an electric potential difference between the P-well 101 at the bottom of the gate 103 and the ground terminal 16. When the electric potential difference becomes greater than a threshold voltage of the parasitic NPN transistor 17, the parasitic NPN transistor 17 is in a conductive state. In this case, current flows from the drain region 102 to the source region 104 to discharge the electrostatic charge accumulated on the I/O interface terminal 15.
The conventional ESD protection circuit thus has low electrostatic discharge efficiency when performing electrostatic discharge.